1. Technical Field
The present invention relates to a solid-state imaging device having a high quality image and low power consumption.
2. Related Art
As solid-state imaging devices mounted in cellular phones and so forth, there are a charge coupled device (CCD) type image sensor and a CMOS type image sensor. The CCD type image sensor is excellent in image quality, while the CMOS type image sensor consumes lower power and its process cost is low. In recent years, MOS type solid-state imaging devices using a threshold voltage modulation method that combines both high quality image and low power consumption have been proposed. The MOS type solid-state imaging device of the threshold voltage modulation method is disclosed in Japanese Unexamined Patent Publication No. 2001-177085, for example.
In an image sensor, image output is obtained by arranging sensor cells in a matrix and repeating three states of initialization, accumulation and reading. In the image sensor disclosed in Japanese Unexamined Patent Publication No. 2001-177085, each unit pixel has a photo-diode for accumulation and a transistor for reading.
FIG. 15 schematically shows a sectional view of the image sensor disclosed in Japanese Unexamined Patent Publication No. 2001-177085.
In the image sensor shown in FIG. 15, in each unit pixel, a photo-diode 111 and an insulated gate field effect transistor 112 are disposed adjacently to each other on a substrate 120. A gate electrode 113 of the transistor 112 is formed in a ring shape, and a source region 114 is formed at the center of the opening portion of the gate electrode 113. A drain region 115 is formed at the periphery of the gate electrode 113.
Charges (photo-generated charges) generated by light incident through an opening region of the photo-diode 111 are transferred to a P-type well region 116 under the gate electrode 113, and accumulated in a carrier pocket 117 formed in this section. The threshold voltage of the transistor 112 changes by photo-generated charges accumulated in the carrier pocket 117. Thus, a signal (pixel signal) corresponding to incident light is obtained from the source region 114 of the transistor 112.
Incidentally, in order to reduce degradation of device characteristics caused by hot electron injection and so forth, a transistor formed on the substrate has an light doped drain (LDD) structure. The LDD structure lowers an impurity concentration of a channel near a gate electrode, compared to the impurity concentration of the channel near a source-drain.
In order to adopt such an LDD structure, a sidewall is formed on a side wall of a gate electrode. By using the gate electrode before the sidewall is formed as a mask, ion-implantation with a low impurity concentration is implemented, and by using the gate electrode after the sidewall is formed as a mask, ion-implantation with a high impurity concentration is implemented.
In order to form such a sidewall on the side wall of the gate electrode, an anisotropic etching is performed after an oxide film and so forth, which becomes a material for the sidewall, is deposited on the entire surface of the substrate.
But there is a problem in that defects may occur in a sensor cell due to damage in the substrate caused by performing the anisotropic etching.